代写DGUT-Cnam Courses、代写Java编程语言、代做Java语言、代做System Design

日期：2019-06-30 10:02

DGUT-Cnam Courses: Computer System Design & Analysis – Java Programming

Computer System Design & Analysis

Java Programming

This project is common to both courses Computer System Design & Analysis and Java Programming.

It has to be realized by the same groups of two students than for project 1. This document describes

the expected work, the deadline, and the conditions to hand in your work.

The project is due on July, 5th.

The aim of the project is to write a simulator of a MIPS processor. You will have to reuse the bits

vector structure of your Project 1 as well as conversion functions.

This project is divided in 5 parts:

1. Register emulation

2. Register banks emulation

3. Multiplexer emulation

4. ALU emulation

5. Processor emulation

Part 1 Registers

A 16 bits register allow to store a binary word of 16 bits. It is composed of 16 registers of 1 bit. The 1

bit register is the elementary memory unit.

(b) a 16 bit register

Figure 1: Registers representation

A 1 bit register has three inputs:

– a 1 bit data input Din

– a 1 bit write enable signal WE

– a 1 bit clock signal CK

and a 1 bit data output.

The data output Dout displays the value stored in the register’s memory.

– When WE = 1, on CK raising edge, the register store the value of Din in it’s memory and update

it’s output accordingly

– In any other conditions (WE = 0 or not CK raising edge instant), the register ignores Din values and

displays the value which is memorized

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DGUT-Cnam Courses: Computer System Design & Analysis – Java Programming

Question 1: Create a Java class which correspond to a 1 bit register specification.

Question 2: Create a Java class which implement a 16 bits registers using the 1 bit register class.

Question 3: propose a UML class diagram of the classes you created.

Remark: A 16 bits register is 16 1 bit registers which have the WE and CK in common (figure 1b).

Therefore, you may also create somes classes to represent the clock signal CK and the WE signal, so that

all the 16 1 bit registers share the same object CK and the same object WE

Remark 2: The clock does not appear in the remaining of this document, but it is an implicit input

of all registers.

Part 2 Register Bank

Figure 2: a register bank

A register bank is a collection of n registers. Each register in the register

bank is designated by its rank number (form 0 to n ? 1).

The register bank supports two operations: writing in a register,

reading from two registers.

The register bank takes as input two register numbers outA and

outB for reading, a register number, in, that designates the register

that is written, a writing enable flag W E and the value of Rin. The

output are the values of registers RA and RB.

Question 1: Implement a register bank of sixteen 16bits registers

using register implementation from part Part 1. If your solution

involves more than one Java class, give the corresponding UML class diagram.

Part 3 Multiplexer

Figure 3: a 16 entries multiplexer

A multiplexer select a value between its multiple inputs: A n inputs

multiplexer has n + 1 inputs:

– n input values i0 to in?1

– a selector s which select one value out of the n inputs and display

it on its output o

Each input values are on 16 bits.

Question 1: implement a n inputs multiplexer. Each input are on

16 bits. Give the corresponding UML class diagram.

Part 4 ALU Emulation

An Arithmetic and Logical Unit compute arithmetic and logical operations

on its inputs.

The ALU posses 3 inputs:

– 2 operands A and B on 16 bits

– a command cmd on 3 bits (could be extended if needed)

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DGUT-Cnam Courses: Computer System Design & Analysis – Java Programming

Figure 4: an ALU

And 4 outputs:

– O: result of the operation

– Z: zero flag, which is 1 when the result if zero, and 0 otherwise

– OV F: overflow flag, which is 1 on overflow, 0 otherwise

– C: carryout flag, which is 1 on carry on the most significant bits,

0 otherwise

The ALU should provide, at least, the following operations:

– Unsigned addition

– Signed addition

– Logical Shift to the right

– Logical Shift to the left

Question 1: give an encoding of each operation for the cmd input.

Question 2: Implement the ALU.

Remark : You are asked to use inheritance to implement the ALU. For instance you may create a class

representing an operation and extend it by creating subclasses for each concrete operation (additions

and shifts).

Part 5 Processor Emulation

Question 1: By using components made in previous part, implement a processor corresponding to the

following architecture. All values should be stored using the bit vector representation of the project 1.

Give the corresponding UML class diagram.

SelA SelB cmd

Seli

Figure 5: Processor Architecture

The processor has 9 inputs:

– Rs, Rt and Rd: specify the source register, the transfer register and the destination register

– Imm: the immediate value

– W E: write enable, enable writing in destination register

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DGUT-Cnam Courses: Computer System Design & Analysis – Java Programming

– Seli

: select the input value of the bank register

– SelA and SelB: select the inputs value of the ALU

– cmd: specify the operation computed by the ALU

and 2 outputs: the result of the ALU and status which is the set of flags of the ALU.

Question 2: Write a small program (a Main class) which allows to test this processor

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