代写IMEL7000/ECEN7003 Fall 2024 Project 3 Fully Differential Two-Stage Miller Op-Amp Design代写C/C++编程

日期：2024-11-21 05:25

IMEL7000/ECEN7003 Fall 2024

Project 3 Fully Differential Two-Stage Miller Op-Amp Design

I. OBJECTIVE

Design a fully differential two-stage operational amplifier (Opamp) as shown in Fig. 1(a) using Cadence/Spectre. This design should include a fully differential two-stage Opamp core with Miller compensation, current mirror based biasing circuit and a common feedback (CMFB) circuit (Fig.   1(b)).   Study and simulate some of the important performance indexes of the Opamp.

Fig. 1. (a) Opamp as a circuit building block. (b) Block Diagram of the Opamp.

II. SPECIFICATIONS

Voltage Supply	VDD=1.2V
DC Gain	AO>55dB (>70dB)
GBW	>500MHz (>1GHz)
Phase Margin	PM>62o
Closed-loop Output Swing	Vo>1.2Vpp differential @1MHz with THD<-40dB (>1.8Vpp differential, THD <-65dB)
Slew Rate	SR>0.5V/ns (>1Vns)
Loading	ZL= CL=1pF
Power Consumption	<8mW (the lower, the better)

** Achieving the specification in brackets indicate bonus.

REMARKS

1. Group project report submission due: 2 December 24:00 (Hard).

2. Group project presentation ppt submission due: 4 December 24:00 (Hard).

3. The filename of your report should be P3_XXXXXXXX.YYY. XXXXXXXX is your student ID and YYY is either doc or pdf. For example, your student number is MC012345, the filename should be P2_MC012345.YYY.

SUPPLEMENTARY

I. DESIGN PROCEDURE

A.  Determine the Topology of the Op-amp

Since an Opamp should have a small output impedance to minimize the load effect, larger part of gain should allocate to the first stage. In this case, you are suggested to use telescopic (cascode) or folded-cascode topology for the first stage. This stage should cover around 40dB gain out of the overall >55dB gain of the whole Opamp. For the second stage, simple common source amplifier can be used to cover the rest of the required gain.

B. Tuning the Operating Point of the Opamp with Ideal Common Mode Feedback

For tuning the operating point of the Opamp, the test bench shown in Fig. 2 can be built. The front part is to generate a differential signal for the input signal of the Opamp. The device ‘xfmr ’ in ‘analogLib’ is used. 10kH inductors are used to act as ideal common mode feedback. Although a 10kH inductor is not practical, it is useful in the beginning stage for designing Opamp. Make sure that the current going through the 2 common mode sources should be small enough (|IS1 |<<ID1  and |IS2 |<<ID2).

One point needs to be concerned is that the input common mode voltage (VCMI) and the output common mode voltage (VCMO2) are suggested to have the same voltage level while the common mode voltage of the first stage can be an arbitrary voltage level.  Otherwise,  some  other  biasing  issues  need  to  be  concerned  in  close-loop configuration.

After the operating point of the Opamp is fixed, you can test the whether the DC gain of the Opamp pass the specifications. Some gain margin should be left for the gain degradation by the common mode feedback resistors (RCMFB).

Till now, the GBW of the Opamp should be much larger than the required 400MHz. Otherwise after the Miller compensation is added to stabilize the Opamp, the GBW of the Opamp drops significantly.

Fig. 2. Test bench for tuning the operating point of the op-amp.

C. CMFB Design

A differential auxiliary amplifier should be designed to act as the CMFB. The ideal CMFB should be removed and connect the op-amp and the CMFB as depicted in Fig. 3. Make sure your common mode feedback signal is a negative feedback signal. DC simulation can be used to make sure your CMFB works well. If the DC levels are acceptable, you should run transient simulation to check whether your CMFB loop is stable (hints: smaller gain of the auxiliary can help the stability of the CMFB loop). (You can even test the phase margin of the CMFB loop to guarantee its stability)

Fig. 3. Op-amp core with common feedback circuit.

D. Biasing Circuit

Till now, you have used the ‘vdc’ to provide the biasing voltage of the transistors. However in practical design, biasing circuit should be design to minimize the effect of process  variation.  Current  mirror  is  used  to   generate  all  the  necessary  biasing voltages.

E. Miller compensation

The Miller compensation is added to the op-amp core to stabilize the op-amp. The RC and CC values influence the phase margin of the op-amp and the GBW. The phase margin should be kept to be large than 60 degrees to guarantee the close loop stability.

II. CADENCE/SPECTRE SIMULATION

A. Open Loop Configuration

Except the CMRR simulation, the test bench of the open loop op-amp is as simple as Fig. 4(a) with a differential signal as the input.

1. DC analysis

We can calculate the power consumption of the op-amp by DC analysis. Moreover, small signal parameters of the transistors can also be observed.

2.AC analysis

We can simulate the differential gain (frequency response) Avd(s) of the op-amp. We can observe the DC gain, GBW and the phase margin of the op-amp from Avd  (s).

3. Common Mode Rejection Ratio (CMRR)

We have obtained the differential gain (frequency response) Avd(s) of the op-amp in the last step. Now we follow Fig. 4(b) to obtain the common mode gain Avc(s). The common mode rejection ratio is defined as

Fig. 4. Open loop configuration with (a) differential input and (b) common mode input.

B. Close Loop Configuration

Figure 5 shows the schematic of an inverting amplifier. Let R1=1kΩ, R2=5 kΩ and CL=1pF.

1.   Transient Analysis

We can simply observe the close-loop stability of the op-amp by transient analysis.

2.   Frequency Response

Using  AC  analysis,  you  can  simulate  the  frequency  response  of  the  inverting amplifier. What is the GBW of the inverting amplifier?

3.   Slew Rate

Use the ‘vpulse ’ in ‘analogLib ’ to generate a steep square wave. We can observe the maximum slope of the output signal to be the slew rate.

Fig. 5. Inverting amplifier using op-amp.

C. Layout (optional bonus for ECE students)

After finishing all the schematic design, it is recommended for the students who have  enough  time  to  draw  the  corresponding  layout,  as  a  bonus  point.  The corresponding layout  should be well drawn with verified DRC/LVS, and the post layout  simulation  result  should  be  included  in  your  report.  A  complete  layout  is preferred, but if time is limited, the top-level integration could be skipped and you can only layout the specific building block that designed by you. For example, if you have finished a common mode amplifier, it’s acceptable for you to only draw this part. But the higher the degree of completion, the higher your score.

III. USEFUL CIRCUIT TECHNIQUES FOR REFERENCE (optional bonus)

The following circuit techniques may help improve the performance. You may choose either one technique and elaborate the operation mechanism and discuss the functional advantage in your project report. (This part is optional)

A. Gain and slew rate enhancement

Ref:  A.  P.  Perez,  Y.  B.  Nithin  Kumar,  E.  Bonizzoni  and  F.  Maloberti,  "Slew-rate  and  gain enhancement  in  two   stage  operational  amplifiers,"  2009  IEEE  International   Symposium  on Circuits     and      Systems      (ISCAS),     Taipei,      Taiwan,     2009,      pp.      2485-2488,     doi: 10.1109/ISCAS.2009.5118305.

B. Class AB output stage

Fig. 6

Ref:  R.   Hogervorst,   J.   P.  Tero,  R.  G.  H.  Eschauzier  and  J.  H.  Huijsing,   "A  compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries," in  IEEE  Journal  of  Solid-State  Circuits,  vol.  29,  no.   12,  pp.   1505-1513,  Dec.   1994,  doi: 10.1109/4.340424.