Number Conversions (12 Points)

Show all of the work necessary to make these conversions

1. Convert 10.12510

to binary.

2. Convert (373.28125)10

to hexadecimal.

3. Convert (BEEF)16

to binary.

4. Convert (101110101110)2

to hexadecimal.

5. Convert (-173.28125)10

to floating point. Use 127 as an exponent bias. Make sure to list

the sign bit, 8 biased exponent bits, and the 23 fractional bits. Use IEEE 754 Floating

Point Format. Convert the 32 bits result into 8 hexadecimal symbols.

6. Convert (17.125)16

to floating point. Use 127 as an exponent bias. Make sure to list the

sign bit, 8 biased exponent bits, and the 23 fractional bits. Use IEEE 754 Floating Point

Format. Convert the 32 bits result into 8 hexadecimal symbols.

Arithmetic (8 Points)

7. Convert the following two numbers into floating point format.

a. 14,760,626

b. 175,663

Show how these two floating point numbers could be added together, by following the

process listed on page 258 of the textbook. Show the intermediate step for each stage of the

addition. Check the final answer by converting the final floating point sum back into the decimal

number system.

CMOS (10 Points)

Draw and label the CMOS construction of a NOT, 2-input NAND, 2-input AND, 3-input NOR,

and a BUFFER.

Canonical and Standard Forms (10 Points)

Here is the canonical expression for a piece of combinational logic to create the output Y.

Y (A,B,C) = ∑ 0, 3, 4, 5

● Draw the logic diagram for the standard form for output Y, using only NOT, AND, and

OR gates. Do not do any minimizations.

● Draw the logic diagram for the minimized form for output Y, using only NOT and NAND

Gates.

● Draw a custom gate for output Y, using only a custom implementation of CMOS. Do not

design this block using gates and then replace the gates with CMOS. Go directly to an

optimized CMOS implementation discussed in chapter 1.

How many transistors are used for each of the 3 diagrams?

Sequential State Machine (20 points)

Design and create a custom Moore State Machine counter that operates in the following manner.

This is testing chapter 3 content, so System Verilog is not allowed for this problem.

● It has a positive edge triggered clock, clk

● It has an active low reset, reset_n. The count is asynchronously reset to 0 when reset_n is

triggered.

● It counts up by 2 when the ud input is 1.

● It counts down by 1 when the ud input is 0.

● The maximum count is 6 and the minimum count is 0. If the current count is 4 and the

counter counts up two , the next value is 6. If it counts up again, the value is capped to 6.

● The output, P, is high whenever the count is a multiple of 3 (3 and 6).

Provide the following artifacts demonstrating your design.

1. State diagram

2. State transition table

3. Output table

4. Logic diagram, showing the gate level design for Next State Logic and Output

Logic. Specifically show how those two blocks are connected to individual flip

flops.

Extra Credit (10 points)

Draft your custom Moore State Machine into Quartus, create a HDL module from your block

diagram file, simulate it in ModelSim to validate your design. Attach a screenshot that

demonstrates correct functionality.

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