CST205留学生代做、代写Digital Logic、代做C/C++，JAVA编程语言

日期：2018-12-24 11:13

description of cOURSEWORK

Course Code CST205

Course Name Digital Logic

Lecturer Soh Chit Siang

Academic Session 201809

Assessment Title Assignment

A.Introduction/ Situation/ Background Information

This assignment consists of two questions. Question 1 is related to the design of synchronous sequential circuit and Question 2 is related to the design of asynchronous sequential circuit. Your tasks are to design the two systems given the design problems and simulate the outputs using LOGISIM software. Show all your design steps, description of the operations of the systems and explanations of the simulation outputs in an assignment report.

B.Course Learning Outcomes (CLO) covered

At the end of this assessment, students are able to:

CLO 2Analyze and design combinational and sequential logic circuits

C.University Policy on Academic Misconduct

1.Academic misconduct is a serious offense in Xiamen University Malaysia. It can be defined as any of the following:

i.Plagiarism is submitting or presenting someone else’s work, words, ideas, data or information as your own intentionally or unintentionally. This includes incorporating published and unpublished material, whether in manuscript, printed or electronic form into your work without acknowledging the source (the person and the work).

ii.Collusion is two or more people collaborating on a piece of work (in part or whole) which is intended to be wholly individual and passed it off as own individual work.

iii.Cheating is an act of dishonesty or fraud in order to gain an unfair advantage in an assessment. This includes using or attempting to use, or assisting another to use materials that are prohibited or inappropriate, commissioning work from a third party, falsifying data, or breaching any examination rules.

2.All the assessment submitted must be the outcome of the student. Any form of academic misconduct is a serious offense which will be penalised by being given a zero mark for the entire assessment in question or part of the assessment in question. If there is more than one guilty party as in the case of collusion, both you and your collusion partner(s) will be subjected to the same penalty.

D.Instruction to Students

1.This is a group assignment with maximum TWO (2) students in ONE group. Write the tasks and works carried out by each member of the group in your assignment report.

2.One hardcopy of assignment report is to be submitted per group.

3.Submit the softcopies of LOGISIM design files (.circ) by email to chitsiang.soh@xmu.edu.my. Name the files with the name of one of the members of the group. Write the header/title of the email as “CST205 Assignment by <names of all the members>”.

4.The assignment report must not exceed 8 pages (not including cover pages and appendices).

5.Deadline for submission of assignment report and LOGISIM .circ design files is 24th December 2018.

E.Evaluation Breakdown

No.Component TitlePercentage (%)

1.Question 1: Synchronous Sequential Circuit Design50

2.Question 2: Asynchronous Sequential Circuit Design50

TOTAL100

F.Task(s)

1.Design a 3-bit binary up/down counter using D flip-flops and Moore machine. The counter counts up when input x = 0 and counts down when input x = 1. The counting up sequence is 000, 001, 010, 011, 100 101, 110, 111 and then repeats. The counting down sequence is the opposite direction of the count up sequence.

Explain and show all your design steps from state diagram to schematic circuit diagram.

Next, simulate your schematic circuit diagram on LOGISIM software to validate that your design is functioning correctly.

2.An asynchronous sequential circuit has one input x and one output z. Design the asynchronous circuit with the following operations shown in timing diagram below

Figure Q2

Use combinational feedback logic circuits and Moore machine. Explain and show all your design steps leading to the schematic circuit diagram.

Validate your design using LOGISIM software.

APPENDIX 1

Marking Rubrics

Component TitleQuestion 1: Synchronous Sequential Circuit DesignPercentage (%)50

CriteriaScore and DescriptorsWeight (%)Marks

Excellent

(5)Good

(4)Average

(3)Poor

(2)

Design Steps All steps are shown in correct order and in proper format, the results of design are correct, with software validationMost steps are shown in correct order and in proper format, the results of design are correct, with software validationMost steps are shown or minor mistakes in design steps, minor formatting mistakes or results, with software validationMissing steps in design, serious formatting errors, results are incorrect, incomplete or wrong software validation.25

Explanation of design/

simulation proceduresComplete, correct and detailed explanation of every steps, sufficient use of diagrams, figures and labelling where necessary.Complete and correct explanation, but required more detailed description in some steps, occasional use of diagrams, figures and labelling.Complete explanation of steps but not detailed with minor mistakes in description, not sufficient labelling in diagram/figuresIncomplete and incorrect explanation of procedures, missing diagram, figure, labelling.10

Spelling, grammar and sentence structureAll grammar/spelling correct and very well-writtenSome minor mistakes in sentence structure but nor affecting the presentation of ideasOccasional grammar/spelling errors, generally readable with some rough spots in writing styleFrequent grammar and/or spelling errors, writing style is rough, sentence structure is difficult to understand10

Appearance, Formatting and Organization of AnswerAll sections in order, well-formatted, very readableMost sections in order, formatting generally good, formatting is rough but readableMost sections in order, contains the minimum allowable amount of handwritten copySections out of order, too much handwritten copy, sloppy formatting, missing pages or pages out of order5

TOTAL50

Note to students: Please print out and attach this appendix together with the submission of coursework

APPENDIX 2

Marking Rubrics

Component TitleQuestion 2: Asynchronous Sequential Circuit DesignPercentage (%)50

CriteriaScore and DescriptorsWeight (%)Marks

Excellent

(5)Good

(4)Average

(3)Poor

(2)

Design StepsAll steps are shown in correct order and in proper format, the results of design are correct, with software validationMost steps are shown in correct order and in proper format, the results of design are correct, with software validationMost steps are shown or minor mistakes in design steps, minor formatting mistakes or results, with software validationMissing steps in design, serious formatting errors, results are incorrect, incomplete or wrong software validation.25

Explanation of design/

simulation proceduresComplete, correct and detailed explanation of every steps, sufficient use of diagrams, figures and labelling where necessary. Complete and correct explanation, but required more detailed description in some steps, occasional use of diagrams, figures and labelling. Complete explanation of steps but not detailed with minor mistakes in description, not sufficient labelling in diagram/figuresIncomplete and incorrect explanation of procedures, missing diagram, figure, labelling. 10

Spelling, grammar and sentence structure All grammar/spelling correct and very well-written Some minor mistakes in sentence structure but nor affecting the presentation of ideas Occasional grammar/spelling errors, generally readable with some rough spots in writing style Frequent grammar and/or spelling errors, writing style is rough, sentence structure is difficult to understand 10

Appearance, Formatting and Organization of Answer All sections in order, well-formatted, very readable, numbering of pages, sections etc.Most sections in order, formatting generally good, formatting is rough but readable, numbering of pages, sections, etc. Most sections in order, contains the minimum allowable amount of handwritten copy Sections out of order, too much handwritten copy, sloppy formatting, missing pages or pages out of order 5

TOTAL 50

Note to students: Please print out and attach this appendix together with the submission of coursework