COMP2120A代写、代做Computer Science、Java，Python/c++编程语言代做

日期：2020-04-21 10:29

THE University of Hong Kong

Department of Computer Science

COMP2120A Computer Organization

Mid-Term Test

Date: 17 April 2020 Time: 9:30am – 11:15pm

Time allowed: 1 hour 45 minutes

This paper contains 6 questions on 4 pages.

Answer ALL questions. Total mark is 60.

1. (a) Write down the full name of MIPS (for benchmarking). Explain why MIPS

count is not a good performance index in one sentence. [2]

(b) While chip density increase enormously, the CPU instruction set becomes less

complex. Suggest two ways how we can use the extra chip space to make CPUs

run faster. [2]

(c) Consider a byte 10111001 Write down the odd parity bit for the following: [3]

(i) for the entire byte.

(ii) for all even bits (the rightmost bit is bit 0).

(iii) for all odd bits

(d) If odd parity is used, what is the value of the missing bit x in 110x00111 if that

bit is dead? [2]

(e) Write down the logical expression corresponding to the following truth table.

(Simplification of the expression is not required) [2]

2. (a) Write down the value of the bit pattern (when treated as unsigned integer) for

the 2’s complement of N,

where N > 0. [1]

(b) When we add two 32-bit unsigned integers together, what is the value of the

carry out from the leftmost bit during addition. (not 1 or 0, but in terms of 2k,

for some k) [2]

(c) Show that when we perform unsigned integer addition to the 2’s complement of

A

and B,

where A > 0 and B > 0, and ignore carry out from the leftmost bit,

we get the 2’s complement of (A

+ B), assuming that there is no overflow. [4]

(d) Write down the condition for overflow in 2’s complement addition. [2]

3. A machine uses 32-bit floating point representation.

S 9-bit Exponent(E) 22-bit Significand(M)

The value is given by :

V = (1)S1.M

⇥ 2Eb

(a) Write down the value of the bias b in exponent in the excess-b representation. [2]

(b) Explain why the significand can be written in the form of 1.M [2]

(c) Write down the value represented by the bit pattern c03e8000 (hex). [3]

(d) Write down the bit pattern representing the value 25.0625. [3]

4. Consider a hypothetical machine with 64K words of cache memory, with cache block

size of 64 words. (1K=1024)

(a) How many blocks are there in the cache memory? [2]

(b) How many sets are there in the cache memory if

(i) Direct-map cache organization is used? [1]

(ii) Two-way set associative cache organization is used? [1]

(c) Write down the number of bits in each field for a 32-bit address. (The address

is byte address, i.e. each address is one byte, and one word is four bytes)

Cache tag Cache Set Number O↵set in the block

for both direct-map and two-way set associative cache. [4]

(d) Calculate the average memory access time if the cache hit time is 9ns, cache

miss penalty is 120ns and the cache hit rate is 95%. [3]

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5. (a) If the rotational speed of the harddisk is R rpm, write down the average rotational

latency of the harddisk. Explain. [3]

(b) Explain why harddisk defragmentation is required. [1]

(c) Write down, in increasing order of CPU intervention, the three types of Input/Output

techniques. [2]

6. Given the data path shown below.

(a) Write down the use of the registers PC, MAR/MBR and IR [3]

(b) What are the two basic operation in the CPU? [2]

(c) Describe the basic operations involved when reading the next instruction into

IR (Instruction Fetch). [2]

[For example: first step is to move the value of PC to MAR via ···]

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(d) Describe the basic operations involved in executing the instruction

ADD R1, R2, R3

where R1 and R2 are the source registers, and R3 the destination register. [4]

(e) To save cost, the designer decided to use one single CPU bus, instead of three.

Write down how the performance of the CPU will be a↵ected. [2]

*** END OF PAPER ***

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