代写EECS112L Organization of Digital Computer Lab代写Java编程

日期：2024-11-10 09:59

Organization of Digital Computer Lab

EECS112L

Lab #: Lab Title

1 Objective

Give a brief summary or a high-level overview of the design. Use a block diagram for your design to explain inputs, outputs and the relation between them. If your design has more than one module, explain how they are related.

2 Procedure

In this section describe how you implement the project in Verilog. A truth table helps to find the boolean equation (if you want to use logical operators), or in general the relation between inputs and outputs. For more complex designs you can also draw the schematic of your design. The schematic of design includes the components of the design and their connectivity. You can use any software like Visio for drawing your designs. For example if you want to design a 4-bit Full Adder using four 1-bit Full Adder components, the schematic would be like this:

3 Simulation Results

Here talk about the expected result. Explain your test cases and how you design them to cover all combinations of inputs. Put the screenshot of your simulation here. You may put one image which contains all test cases or several images (if they are not clear in one image ). Also, define the signals in the screenshots and explain how and when changes in the inputs make changes in the output. If there is something different from what you expect, explain why.

4 Written questions

Add here any lab specific questions.