代写ELEC6230 VLSI Systems Design Coursework调试SPSS

日期：2024-08-03 05:56

VLSI Systems Design Coursework

Bitslice Datapath Design

• Working individually.

• Implement an 8 bit multiplier datapath using bitslice techniques.

• Implement a synthesizable SystemVerilog control unit for your datapath.

One option:

1. Datapath Architecture and Algorithm Provided, Control Signals Specified

Cell library

• Combinational Cells

mux2  fulladder  halfadder  inv

and2  or2  nand2  nor2  xor2

nand3  nor3  nand4

buffer  trisbuf

• Sequential Cells

scandtype  scanreg

8 bit Multiplier Datapath - TYPE#1

Datapath Architecture

Multiplication Algorithm - TYPE#1

• The datapath has been designed to implement the following simple multipli- cation algorithm:

A  =  0;

B  =  Operand1; M  =  Operand2;

while   (  M   !=  0  ) begin

M  =  M  -  1; A  =  A  +  B;

end

B=0;

Result  =  B  +  A;

Implementaion of Blocks

• Each 8-bit register is implemented as 8 scannable register cells.  The signals Clock,nReset, Test etc are not shown to keep the datapath diagram simple.

• The 8-bit adder is implemented as a ripple carry adder based on 8 full adder cells.

• The decrementer:

The decrementer can be constructed from a number of half subtractors. Each half subtractor is built from a half adder and two inverters.

8 Identical Bitslice Cells

• all inter-bitslice wiring is by butting.

Datapath Cell

inputs:    Clock,nReset, Test, SDI,LoadA, LoadB, LoadM, LoadR, EnableAdder, EnableZero, EnableOp1,SelOp2, Operand1, Operand2

outputs:  SDO,Result, Underflow

• control – synthesizable behavioural model generates control signals

• multiplier – structural model instances datapath and control

• multiplier stim – test harness.

To indicate that a new multiplication is required, the stimulus will raise the Req signal for one clock cycle. Once the Result becomes available, the control module will raise the Done signal for one cycle.

Bitslice Datapath Design – Synthesis, Place & Route

• control – Synthesis

You should synthesize the control unit and verify that the synthesized gate- level version works in place of the behavioural version.

• control – Place & Route

You should place and route the control unit and verify that the netlist extracted from magic version works in place of the behavioural version.

Location of magic files

• Cell Library Directory

All magic leaf cells (leftbuf .mag,  rightend .mag,  fulladder .mag . . . ) should exist only in the cell library directory:

˜/design/magic/tsmc180/cell_lib

• Bitslice Directory

The magic hierarchical cells (bitslice.mag, datapath.mag, control.mag) should exist only in the bitslice directory:

˜/design/magic/tsmc180/bitslice

To enable access to the leaf cells when creating a hierachical cell you will need to use the magic addpath command:

:addpath  /home//design/magic/tsmc180/cell_lib before using the :getcell command.

The easiest way to do this is to include the appropriate addpath command in a ” .magicrc” file in the bitslice directory. This is done automatically by the script.

init_bitslice_directories

Location of SystemVerilog files

• Behavioural Directory

- control .sv  control stim .sv

- multiplier .sv  multiplier stim .sv  multiplier .tcl ˜/design/magic/tsmc180/bitslice/behavioural

• Gate Level Directory

- control .sv

˜/design/magic/tsmc180/bitslice/gate_level

• Extracted Directory

- control .vnet  control .sv  control stim .sv

- bitslice .vnet  bitslice .sv  bitslice stim .sv

- datapath .vnet  datapath .sv  datapath stim .sv   ˜/design/magic/tsmc180/bitslice/extracted

Submission – Files

Prepare script. (prepare_vlsi  supplementary) will collect the magic and Sys- temVerilog files into a single handin.tar file.

The script. will also run a number of simple simulations.

Submission – Supporting Figures

System design diagrams (in each case all control signals must be shown):

• Bitslice Gate Level Schematic                  single A4 page PDF document readable at A5 size

• ASM Chart                                                single A4 page PDF document readable at A5 size

• Both figures combined on one page       single A4 page PDF document