代做Computer Systems Architecture 2023/24 Cache controller simulator Part 1代做Statistics统计

日期：2024-05-13 08:14

Computer Systems Architecture 2023/24

Laboratory Exercise - Cache controller simulator Part 1

1. Introduction

The Computer Systems Architecture laboratory exercise has two parts. In the first part you will    write and validate a C program to simulate the operation of a direct mapped cache controller on an embedded processor. In the second part, you will use your simulator to analyse the impact of cache memory size and cache memory block size on the performance of the embedded system   when executing a sample program.

You will work individually on this laboratory exercise; submitting a C program, a memory trace file used for validation and a short report.

2.   Embedded system memory architecture

The embedded processor is interfaced to a 256 Ki x 16-bit external data memory using a 20-bit address bus and a 16-bit data bus. The embedded processor contains a direct mapped cache controller for data accesses. The cache controller can be configured for cache sizes between 4 and 256 blocks and for cache block sizes between 2 and 32 16-bit words. The cache controller implements a Write-Allocate / Write-Back write policy.

3. Cache controller simulator

Write a structured program in C to simulate the operation of the data cache controller in the embedded processor.

The program must read three parameters from the terminal window command line as shown below.

cachesim tracefilename cacheblocks blockwords

tracefilename the filepath for the memory trace file

cacheblocks a decimal integer specifying the number of blocks in the cache memory

blockwords a decimal integer specifying the number of words in a cache memory block

The program must validate the command line parameters.

The simulator must output its results on a single line in the terminal window in the format specified below. All values must be presented as unsigned integers separated by commas.

CPUR, CPUW, NRA, NWA, NCRH, NCRM, NCWH, NCWM

CPUR Total number of CPU read accesses

CPUW Total number of CPU write accesses

NRA Total number of read accesses to the external (main) memory

NWA Total number of write accesses to the external (main) memory

NCRH Number of cache read hits

NCRM Number of cache read misses

NCWH Number of cache write hits

NCWM Number of cache write misses

The simulator program must be suitable to be run from a terminal window, reading simulation parameters from the command line, and writing formatted simulation results to the terminal window without additional user input. The program must be written to comply with the ANSIC17 standard of the C programming language.

The program must include a comment header which includes your name and student ID number. The program must be clearly commented and use descriptive function and variable names.

It is strongly recommended that you construct a software flowchart for the operation of the cache controller, and then directly code this in C.

The program must not be stored in a software repository, such as GitHub, with shared access.

4. Memory trace files

Memory trace files record the values of the CPU address and data buses for each read and write access made by the CPU. The accesses are recorded in the order that they occur.

The memory trace file is an ASCII text file where each line records either a read or write memory access, or is acomment. The line formats are specified below.

R˽address˽data

W˽address˽data

!comment

The R, W and ! characters must be in the first character column of a line. The ˽ symbol represents a single space. The address and data values are specified in hexadecimal and may be up to 8

hexadecimal digits in length. Blank lines are ignored.

5.   Validating your cache controller simulator

Create a memory trace file to validate the operation of your cache controller simulator. The trace file should exercise all the decision paths in your program. The memory trace file must include a comment header which includes your name and student ID number. Clearly comment all sections of the memory trace file to indicate what each section is validating.

Appendix A presents some useful guidance on creating memory trace files to validate your simulator.

6. Assessment

There are two elements to the assessment of the first part of the laboratory exercise. They combine to contribute 10% towards the overall unit mark.

6.1. Cache controller simulation program

The cache simulation program must be submitted to Blackboard as a single ASCII file using the submission link that can be found in the Laboratory Materials folder. The filename must conform to the format familyname_studentIDnumber_cachesim.c

Example: Green_1234567_cachesim.c

The program will be compiled and run to verify that it executes correctly. Any source code that you have not authored, including that generated by AI, must be clearly identified and referenced. The program will be submitted to a source code plagiarism detection tool.

The criteria for the assessment of the cache controller simulation program, together with indicative percentage marks, are given below:

• Functional correctness 70%

•    Use of appropriate structured programming techniques 10%

•    Readability, including clear comments 20%

6.2. Memory trace file used for validation

The memory trace file used for validation must be submitted to Blackboard as a single ASCII file using the submission link that can be found in the Laboratory Materials folder. The filename must conform. to the format familyname_studentIDnumber_validation.txt

Example: Green_1234567_validation.txt

The memory trace file will be submitted to a plagiarism detection tool.

The criteria for the assessment of the memory trace file used for validation, together with indicative percentage marks, are given below:

•   Completeness of validation 80%

•   Clarity of commenting                 20%

6.3. Submission Deadlines

You have been allocated to one of two laboratory groups. Group A has laboratory sessions scheduled in weeks 6 and 8, and Group B has laboratory sessions scheduled in weeks 7 and 9.

The submission deadlines for the cache simulation program and the memory trace file used for  validation areas follows. There are no automatic DASS extensions available for these deadlines.

Group A:           17:00 (UK time) on Friday 12th April 2024.

Group B:           17:00 (UK time) on Friday 19th April 2024.

Peter R Green

Version 1.0   15th  February 2024.

Appendix A - Validating your cache controller

With careful choice of the cache parameters, it is possible to create a memory trace file to validate your simulator without complex address calculations.

If we simulate a cache memory with 256 blocks, each containing 16 words, then the process of creating 20-bit processor addresses from the Block Offset, Cache Memory Block ID and the Tag Bits is relatively straightforward. The Block Offset is a 4-bit value (24  = 16 words in a block) and maps to one hexadecimal digit. The Cache Memory Block ID is an 8-bit value (28  = 256 blocks) and maps to two hexadecimal digits. Lastly, there are the 8 Tag Bits, and these map to two hexadecimal digits.

Below is an example of how a Block Offset of 0x5,a Cache Memory Block ID of 0x83, and the Tag Bits 0x0C form. the CPU address 0x0C835.

A19

A12

A11

A4

A3

A0

Tag Bits

Cache Memory Block ID

Block Offset

0	0	0	0		1	1	0	0	1	0	0	0	0	0	1	1	0	1	0	1
0				C					8				3				5

Example 1: Validate cache hit counting

By keeping the Cache Memory Block ID and the Tag Bits constant we can generate a sequence of cache hits. There will also be one cache misson the initial loading of the cache block following reset.

! cache miss; 16 words moved from external memory to cache memory

R C835 0000

! 4 cache hits

R C836 0000

R C837 0000

R C838 0000

R C839 0000

Example 2: Validate write back of cache blocks

By writing to a block in the cache and then triggering it being overwritten we can test the implementation of the Dirty bit logic.

! cache miss; 16 words moved from external memory to cache memory

R C835 0000

! cache hit; sets dirty bit

W C835 0000

! cache miss; 16 words moved from cache memory to external memory ! 16 words moved from external memory to cache memory

R D830 0000

If you wish to validate your program with a different block size, then you can simulate a cache memory with 16 blocks, each containing 256 words. This configuration again maps conveniently to hexadecimal address digits.